LUT Hybrid + CORDIC
Hybrid lookup + CORDIC engine for fast trig, vector rotation, and magnitude with low LUT/DSP footprint.
- Functions: sin/cos/atan2, rotate, magnitude
- Parametric precision & pipeline depth
- FPGA‑friendly resource utilization
About Vyomex
Vyomex builds next‑generation semiconductor IP cores designed for performance, scalability, and efficiency. We deliver RTL, testbenches, integration guides, and direct engineering support so teams can tape‑out faster with confidence.
IP Cores
CAN 2.0B + AXI
ISO 11898‑1 compliant CAN controller with AXI4‑Lite interface for seamless SoC integration.
- Bit timing, filters, error handling
- AXI4‑Lite register map
- Loopback & self‑test modes
DPLL with CORDIC
Digital PLL featuring a CORDIC‑based NCO for precise phase/frequency tracking and low jitter.
- Wide lock range with lock detect
- CORDIC NCO for fine resolution
- AXI‑ready control registers
LUT Hybrid + CORDIC — Details
A hybrid math engine combining small lookup tables with iterative CORDIC stages to deliver high‑throughput trig and vector operations with predictable latency and excellent FPGA utilization.
| Parameter | Typical | Notes |
|---|---|---|
| Functions | sin, cos, atan2, rotate, |v| | Fixed‑point |
| Latency | Configurable (N cycles) | Pipeline depth parameter |
| Throughput | 1 sample / cycle | At max clock |
| Interfaces | AXI4‑Lite / SPI | Ready/valid |
| Resources | LUT/FF/DSP minimal | Depends on width |
CAN 2.0B + AXI — Details
Robust CAN controller compliant with ISO 11898‑1, exposed via an AXI4‑Lite register interface for fast bring‑up in FPGA and ASIC SoCs. Includes acceptance filters, error counters, and loopback.
| Parameter | Typical | Notes |
|---|---|---|
| Protocol | CAN 2.0B (ISO 11898‑1) | Standard & Extended frames |
| Host Bus | AXI4‑Lite | Memory‑mapped registers |
| Bit Timing | Configurable | Sample point control |
| TX/RX | Mailboxes + FIFOs | Selectable depth |
| Diagnostics | Error flags & counters | Loopback/self‑test |
DPLL with CORDIC — Details
Parameterizable digital PLL featuring a CORDIC‑based NCO for high‑resolution phase accumulation, wide lock range, and low steady‑state jitter. Suitable for CDR and RF baseband tasks.
| Parameter | Typical | Notes |
|---|---|---|
| NCO | CORDIC‑based | Fine phase & freq |
| Loop | PI / 2nd‑order | Programmable gains |
| Lock Detect | Windowed | Programmable thresholds |
| Interfaces | AXI4‑Lite control | Status & tuning |
| Latency | Deterministic | Pipeline dependent |
Why Vyomex?
Performance
Architectures tuned for high Fmax and low resource use.
Architectures tuned for high Fmax and low resource use.
Scalability
Parametric widths, pipeline depth, and buffer sizing.
Parametric widths, pipeline depth, and buffer sizing.
Quality
Linted RTL, self‑checking testbenches, coverage reports.
Linted RTL, self‑checking testbenches, coverage reports.
Support
Integration assistance, customization, and SLAs.
Integration assistance, customization, and SLAs.
FAQ
What deliverables are included?
Source RTL (or encrypted, per license), testbenches, simulation models, integration guide, and example projects. Optional: timing constraints and synthesis scripts.
Do you provide evaluation licenses?
Yes — time‑limited or feature‑limited evaluation is available for qualified teams. Contact support for options.
Which devices are supported?
Common FPGA families (Xilinx/AMD, Intel, Lattice) and ASIC flows. Tell us your target and we’ll confirm.
Contact
Email: support@vyomex.in